This invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a redundancy circuit.
Recently, in semiconductor memory devices, there is frequently employed a redundancy configuration for the purpose of preventing lowering of the yield followed by implementation of devices of large capacity. Namely, with a view to relaxation of lowering of the yield resulting from bit defects, columns defects, or row defects in a chip which occurs during manufacturing process, a spare memory cell array is mounted in advance on the chip to replace unsatisfactory (defective) portions found by inspection by corresponding spare cells to relieve an unsatisfactory chip. As a device including a redundancy circuit as mentioned above, there is a device described in, e.g., 1982 IEEE International Solid-State Circuit Conference Digest of Technical Paper, "A 64 Kb CMOS SRAMs", S.: Konishi, et al., pp. 258-259.
In order to replace a defective bit by a corresponding spare cell of a spare cell array by utilizing the redundancy configuration, in the case where an address signal for selecting a defective cell is inputted from the! exterior, it is necessary to realize a mechanism for providing an access to the spare cell array.
In general, there is employed a method in which fuse elements are formed by using wiring layer, etc. to carry out laser blow to blow off such element by irradiating laser beams thereto, thus to realize such an access mechanism. For example, in a SRAM adapted so that defective cells are relieved, e.g., with the row being as a unit, fuses are arranged between respective word lines and circuits for driving those word lines. In this case, a method is employed such that a fuse provided at a word line of a defective row is blown off in advance by laser beams so that this word line is not activated even if an address signal for selecting it is inputted. For such SRAM, there is a SRAM disclosed in, e.g., the Japanese Patent Application Laid Open No. 18899/1985 (Tokkaisho 60-18899), or the Japanese Patent Application Laid Open No. 20397/1985 (Takkaisho 60-20397).
As a SRAM related to this invention, the configuration of a SRAM where 8 spare rows are arranged in respect to 1024 normal rows is shown in FIG. 12. In this device, word lines are doubly arranged for the purpose of driving normal memory cells MC in a manner divided every sections.
At the end portion of a memory cell array NMA1501, a row main decoder RMD1501 is arranged. At the row main decoder RMD1501, a plurality of series circuits each comprising a NAND circuit NA1501, a word line buffer WB1501 comprised of two stages of inverters, and a defective row isolation fuse FU1501 are provided every normal main word line NWM. To the row main decoder RMD1501, row predecode signals generated by an address decoder AD1601 shown in FIG. 13 are delivered.
As shown in FIG. 13, an address signal of, e.g., 10 bits is inputted from the external to input terminals Ax0-Ax9 of the address decoder AD1601. This address signal is decoded by row predecoders RPD1601, and is outputted as row predecode signals X0.multidot.X1, X0.multidot.X1, . . . . These signals are delivered also to spare row decoders RRD1801 of which detailed configuration will be described later. They are outputted as spare row decode signals from the spare row decoder RRD1801, and are delivered to the spare memory cell array.
In a column direction of the memory cell array NMA1501, a column decoder CD1501 and a section decoder SD1501 are provided in every section.
In FIG. 12, selection in the row direction of the memory cell MC is carried as follows. Row predecode signals are delivered to the row main decoder RMD1501. As a result, any one of 1024 normal main word lines NMW is selected. Further, any section is selected by the section decoder SD1501. As a result, the potential on a word line SW within that (selected) section rises.
Selection in a column direction is carried out in such a manner that any one of the bit lines is selected by the column decoder CD1501.
In the spare memory cell array RMW, spare memory cells of 8 rows are arranged. At the end portion of the spare memory cell array RMW, a spare word line buffer WB1501 for selecting a spare main word line RMW is provided. To the spare word line buffer WB1501, spare row decode signals generated by the above-mentioned spare row decoder RRD1801 shown in FIG. 14 are inputted.
The spare row decoder RRD1801 shown in FIG. 14 is a decoder of the type also disclosed in the Japanese Patent Application Laid Open No. 168900/1988 (Tokkaisho 63-168900), and is adapted so that the above-mentioned row predecode signals X0.multidot.X1, X0.multidot.X1, . . . are inputted thereto. The inputted row predecode signals are inputted to a NAND circuit NA1801 through CMOS transmission gate circuits TG for switch each comprised of a P-channel transistor and an N-channel transistor connected in parallel. The switching conditions (ON/OFF states) of respective gates in the CMOS transmission gate circuit TG for switch are determined by output signals F, F from two sets of fuse selection circuits FS1801 and FS1802. Any one of the gates is opened by the signals F, F. As a result, any one of four predecode signals is passed through that gate and is outputted therefrom.
There are provided a plurality of CMOS transmission gate circuits TG for switch. Respective output signals SP01i-SP89i are inputted to the NAND circuit NA1801. Further, to this NAND circuit NA1801, a spare enable signal SPEi from a spare enable signature circuit SES1701 for selecting any one of plural spare row decoders RRD1801 is inputted.
When the spare row decoder RRD1801 is not selected., the spare enable signal SPEi is at low level. As a result, a spare row decode signal of high level is outputted irrespective of the signals SP01i-SP89i. On the other hand, when the spare enable signal SPEi is at high a level, the level of the spare row decode signal is determined on the basis of signals SP01i-SP89i passed through the respective CMOS transmission gate circuits TG for switching.
The fuse selection circuit FS comprises, as shown in FIG. 15, a fuse FU1701, an inverter IN1701, capacitors C1701 and C1702, and an N-channel transistor N1701. The combination of the levels of signals F varies depending upon whether or not the fuse FU1701 is blown off. In the case where the fuse FU1701 is not blown off, the signal F is at a high level and the signal/F is at low level. Conversely, in the case where the fuse FU1701 is blown off, the signal F is at low level and the signal/F is at high level opposite to the above.
In SRAM having such a configuration, in the case where any one of normal rows is defective, a defective row isolation fuse FU1501 of the row where that defect exists is blown off by laser beams. Thus, even if an address signal which selects this defective row is inputted, an access to the defective row is not provided. In addition, since respective normal main word lines NMW are fixed to a high level by P-channel transistor P1501 of the normally on type as shown in FIG. 12, they maintain a non-selective state without being brought into a floating state.
When this defective row is selected, any spare row is instead automatically selected. For selecting any one of the spare rows, it is necessary to implement fuse blow operation to the fuse selection circuit FS of the spare row decoder RRD1801. As shown in FIG. 14, for selecting one spare row, it is necessary to carry out blowing of 11 fuses in total at the maximum of 10 fuses at the maximum for row predecode signals X0.multidot.X1, x0.multidot.X1, . . . , X8-X9 and one fuse for the spare enable signature circuit SES1701 for selecting the spare row decoder RRD1801.
Among these configurations, only the circuit configurations of the normal main word line(s) NMW and the spare main word line(s) RMW are shown in FIG. 16. As described above, to each of normal main word lines NMW of 1024 rows, a row main decoder RMD1901 comprised of a NAND circuit, a word line buffer WB1501, and a fuse FU1901 are serially arranged. At each of spare main word lines RMW of 8 rows, a word line buffer WB1901 is arranged. The normal main word line NMW and the spare main word line RMW are brought into a selective state when potential thereon are at the low level.
The configurations of the normal main word line NMW and the spare main word line RMW in other SRAM related to this invention are shown in FIG. 17. To the end portion of the normal main word line NMW, a row main decoder RMD2001, an inverter IN2002, a fuse FU2001, and an inverter IN2001 are serially connected. This configuration differs from the configuration shown in FIG. 16 in that fuse FU2001 is connected between inverters IN2001 and IN2002. In the case where the load capacity of the normal main word line NMW is large, a fuse FU having a resistance greater than that of the signal line is provided between inverters IN2001 and IN2002 of the word line buffer WB201, thereby permitting the charging/discharging speed to be higher.
At the node connecting the inverters IN2001 and IN2002, drains of N-channel transistors N2001 and N2002 are connected. Further, sources of the transistors N2001 and N2002 are grounded. The transistor N2001 is such that its gate is connected to the output node of the inverter IN2001, and the transistor N2002 is in a normally ON state. Although the transistor N2001 is not necessarily required, it has the role of providing feedback of the level of the normal main word line NMW 2001 to stably hold the level of the input node of the inverter IN2001. Further, the transistor N2002 is provided for the purpose of securely allowing the input node of the inverter IN2001 to be held at the low level in the case where the fuse FU2001 is blown off, and its drivability is set to a value sufficiently lower than that of transistors constituting inverters IN2001 and IN2002. The normal main word line NMW and the spare main word line RMW are brought into a selective state when potential thereon are at the low level.
The configurations of the normal main word line NMW and the spare main word line RMW in other SRAM are shown in FIG. 18. The normal main word line NMW and the spare main word RMW are brought into a selective state when potential thereon are at high level oppositely to those shown in FIGS. 16 and 17. For this reason, the number of stages of inverters provided at respective word lines is one unlike those in FIGS. 16 and 17. To the end portion of the normal main word line NMW, a row main decoder RMD2101 comprised of a NAND circuit, a word line buffer WB2102 comprised of a single inverter, and a fuse FU2101 are serially connected. To the end portion of the spare main word line RMW, a word line buffer WB2101 comprised of a single inverter is connected.
The configurations of the normal main word line NMW and the spare main word line RMW shown in FIG. 18 correspond to the configurations where the number of stages of inverters is set to one in the word line configurations shown in FIG. 16.
The configurations of the normal main word line NMW and the spare main word line shown in FIG. 19 correspond to the configurations where the number of stages of inverter is set to one in the word line configurations shown in FIG. 17. The normal main word line NMW and the spare main word line shown in FIG. 19 are brought into a selective state when the potential thereon are at a high level similarly to the configuration shown in FIG. 18.
The above-described redundancy circuits are all provided in a row direction. On the contrary, there exist configurations where a redundancy circuit is provided in a column direction. Such a configuration is effective for the purpose of preventing a delay of a word line propagation time and reducing power consumption at the time of operation.
The configuration of a SRAM where normal columns and spare columns are arranged in respective sections SEC91-SEC9N is shown in FIG. 20. Further, the configuration of a SRAM where sections are arranged in such a manner divided into sections SEC1001-SEC100N comprised of only normal columns and sections SEC100N+1 comprised of only spare columns is shown in FIG. 21.
In the circuit shown in FIG. 20, the core region is divided into N sections SEC91-SEC9N, and a memory cell array MCA91, a sense amplifier and write circuit SAW91, and a column gate CG91 are provided within each section.
The memory cell array MCA 91 is comprised of eight 1/01-I/08. Each I/O includes n number of normal columns and s number of spare columns. Thus, s number of normal columns can be relieved every I/O. As the entirety of SRAM, 8.s.N spare columns are arranged.
In the circuit shown in FIG. 21, only normal columns are arranged in normal sections SEC1001-SEC100N, and spare columns are arranged in a spare section 100N+1. In the spare section 100N+1, eight 1/01-I/08 are constructed. Further, s number of spare columns are arranged at respective I/O.
In the circuits respectively shown in FIGS. 20 and 21, isolation in the case where there is any defect in the normal columns is carried out by using a control signal without the use of a fuse. As a control signal, a section decode signal S for selecting the section, a column decode signal C for selecting the column, a column gate signal CG for controlling opening/closing operations of the column gates CG91, CG101, a common bit line select signal CBL for selecting a common bit line, a spare decode signal SPD delivered to a spare decoder, and a spare hit signal SPH indicating that the spare column is selected are used.
Among these control signals, the column decode signal C, the section decode signal S, and the spare hit signal SPH are generated by a circuit as shown in FIG. 22. To a column address input buffer CAB, m number of column address input signals CAI are inputted. Outputs of the column address input buffer CAB are delivered to a column decoder CD 1101, and are outputted as H number of column decode signals C. In addition, outputs of the column address input buffer CAB are delivered also to a fuse selection circuit FS1101. Outputs of the fuse selection circuit FS1101 are delivered to a spare column decoder SCD1101.
On the other hand, n number of section address input signals for selecting the section are inputted to a section address input buffer SAB. Outputs from the buffer SAB are delivered to a section decoder SD1101. As a result, N number of section decode signals S are outputted therefrom. Further, outputs from the section address input buffer SAB are delivered to a fuse selection circuit FS1102. Outputs from the fuse selection circuit FS1102 are delivered to a spare section decoder SSD1101. In this example, the fuse selection circuits FS1101 and FS1102 have a configuration as shown in FIG. 15 similarly to the fuse circuit FS1801 shown in FIG. 14.
As shown in FIG. 22, outputs of the spare column decoder SCD1101 and the spare section decoder SSD1101 are delivered to an AND circuit AND1101, and an output signal SPD(1) of the AND circuit AND1101 is delivered to an OR circuit OR1101. To the OR circuit 1101, s number of such output signals from the AND circuit, which is the number of spare columns, are inputted. This OR circuit OR1101 outputs a single spare hit signal SPH.
An increase of the memory cell array region resulting from the fact that a redundancy circuit is provided in the circuit shown in FIG. 20 and the number of necessary decoders of spare columns are as follows. As described above, since the number of spare columns is 8.s.N, the rate of an increase of the memory cell array region is expressed as (8.s.N)/(8.n.N)=s/n. In addition, s.N number of decoders for spare columns are required.
In the circuit shown in FIG. 21, the increasing rate of the memory cell array region is 1/N and s number of column decoders for spare columns are required.
In the above-described device, in the case where the device is caused to have a redundancy circuit, elements as described below must be added as compared to the device including no such redundancy circuit:
(1) Spare memory cell array and word line buffer PA0 (2) Defective row isolation fuse PA0 (3) Transistor in a normally ON state provided so that the normal main word line after the fuse is blown off is always in non-selective state, without being brought into floating state. PA0 (4) Spare row decoder PA0 (1) Increase of an area by addition of the spare memory cell array and the word line buffer PA0 (2) Increase of an area by addition of defective row isolation fuse PA0 (3) Increase of an area by addition of a transistor in normally ON state PA0 (4) Increase of an area by addition of the spare row decoder
Approximation of the rate where the area is increased by addition of such elements is as follows.
When it is now assumed that a normal memory cell array of 1024 rows is provided and a spare memory cell array of eight rows is added thereto, the area is increased by 0.8% on the basis of the relationship expressed as 1032/1024=1.008.
It is necessary to provide 1024 fuses which have the same number as the 1024 normal rows between the memory cell array and the word line buffer. These fuses must be disposed in the vicinity of the memory cell array. However, in order not to damage fuses and-circuits or wiring therearound in carrying out blowing by laser beams, a distance of about 100 .mu.m is required between fuses and circuits or wiring. The area is increased by a quantity corresponding to this distance.
This transistor may be constituted with a MOS type transistor having an extremely low drivability, or a high resistance element. An increase in the area corresponding to several columns in terms of array only takes place.
In the spare row decoder shown in FIG. 14, the number of spare rows is 11.times.8, and nine sets of decoders including 88 fuses are required. As an approximation, the area of one spare row decoder necessary for one spare row is about 20000 .mu.m.sup.2. Thus, if eight spare row decoders are provided, there would result an increase in the area of about 160000 .mu.m.sup.2.
The number of the fuse blow operations increased by employment of the redundancy circuit configuration will now be described. In Table 1, the number of fuse blow operations relating to the spare row in a SRAM of 64 K bits to a SRAM of 16 M bits is shown.
TABLE 1 __________________________________________________________________________ NO. OF FUSE BLOW PRIOR ART EMBODIMENT DEFECTIVE TOTAL DEFECTIVE ADDRESS (ONLY SPARE ROW ROW PROGRAM DEFECTIVE SRAM BIT NO./NORMAL ISOLATION FUSE ISOLATION DENSITY ROW NO. FUSE BLOW BLOW* TOTAL FUSE BLOW) __________________________________________________________________________ 64K SRAM 2/256 MAX. 2 MAX. 18 MAX. 20 MAX. 2 256K SRAM 4/512 MAX. 4 MAX. 40 MAX. 44 MAX. 4 1M SRAM 8/1024 MAX. 8 MAX. 88 MAX. 96 MAX. 8 4M SRAM 16/2048 MAX. 16 MAX. 192 MAX. 208 MAX. 16 16M SRAM 32/4096 MAX. 32 MAX. 416 MAX. 448 MAX. 32 __________________________________________________________________________ * = [log.sub.2 (normal row No.) + 1] .times. (spare row No.)
Spare rows are provided at a rate of one row to 128 normal rows. By taking an example of 64 Kbit SRAM, two spare rows are provided with respect to 256 normal rows. The number required for blowing a defective row isolation fuse is 2 at the maximum. In the spare row decoder in this case, sum of the number of fuse blow operations required for storing addresses of defective rows and the fuse blow operations for spare row enable is 18 at the maximum. Thus, sum total of the number of fuse blow operations is equal to 20 at the maximum.
As apparent from the Table 1, a greater part of the number of fuse blow operations is occupied by the number of fuse blow operations for storing addresses of defective rows and the number of fuse blow operations for spare row enable. With realization of SRAMs of high capacity, the number of blow operations increases to a large degree.
Explanation has been given in connection with increases of the area and the manufacturing process steps by employment of a redundancy circuit configuration in a row direction. Now, increases of the area and the manufacturing process steps in the case where a SRAM is caused to similarly have a redundancy circuit in a column direction will be described.
As described above, in the circuit configuration shown in FIG. 20, the rate of an increase of the area resulting from the fact that a spare memory cell array is provided is s/n. On the other hand, in the case of the circuit configuration shown in FIG. 21, such a rate is equal to 1/N.
Since a fuse for isolation of a defective column is not used, an increase of the area based thereon is zero. Similarly, since a transistor in a normally ON state is not added, there is no increase of the area based thereon.
In the configuration of FIG. 20, s.times.N number of spare column decoders are required. On the other hand, in the configuration of FIG. 21, s number of spare column decoders are required. When it is assumed that 1024 normal columns and eight spare columns are provided in 1 M bit SRAM of the 8 I/O configuration, a column address required for decoding is 7 bits, so an area of about 15000 .mu.m.sup.2 per one spare column is increased. Thus, eight spare column decoders are required as a whole, so an area of about 120000 .mu.m.sup.2 is increased.
The number of fuse blow operations resulting from the fact that the device is caused to have a redundancy circuit with respect to the column direction is shown in Table 2.
TABLE 2 __________________________________________________________________________ NO. OF FUSE BLOW PRIOR ART EMBODIMENT SRAM BIT SPARE COLUMN TOTAL (ONLY TOTAL (ONLY DENSITY NO./NORMAL DEFECTIVE ADDRESS DEFECTIVE COLUMN (8 BIT SRAM) COLUMN NO PROGRAM FUSE BLOW*) ISOLATION FUSE BLOW) __________________________________________________________________________ 64K SRAM 2/256 MAX. 12 MAX. 2 256K SRAM 4/512 MAX. 28 MAX. 4 1M SRAM 8/1024 MAX. 64 MAX. 8 4M SRAM 16/2048 MAX. 144 MAX. 16 16m SRAM 32/4096 MAX. 320 MAX. 32 __________________________________________________________________________ * = [log.sub.2 (normal column No.) - 2] .times. (spare column No.)
Similarly to the row direction shown in Table 1, spare columns are provided at a rate of one column to 128 normal columns. As apparent from the Table 2, the number of blow operations will increase to a large degree with realization of a device of high capacity although such an increasing rate is not much higher than that in the case where spare rows are provided.
As described above, when a redundancy circuit configuration is employed, an area is increased and the number of manufacturing process steps also increases to a large degree. Thus, there result in an increase of the chip size and an increase of the manufacturing time and/or the manufacturing cost.